In general, CRC (Cyclical Redundancy Check) error-checking involves detecting errors during transmission of data packets. Prior to sending a data packet, a transmitter typically processes the data packet using a complex calculation (based on a polynomial equation) to generate a CRC value. Upon sending the data packet, the transmitter also sends the CRC value along with the data packet for error-checking purposes. A receiver of the data packet and corresponding CRC value typically repeats the same complex error-checking calculation on the data packet. If the receiver generates the same CRC value for the data packet as the CRC value received along with the data packet, it is assumed that the data packet transmission was received error-free.
In one application, each data packet transmitted in a communication system is guaranteed to be a multiple of some word length by padding the packet. In this case, it is a relatively straightforward process to generate corresponding CRC values because data packets are partitioned into equally-sized words for parallel processing. Restricting data packets to a multiple of some word size solely for CRC error-checking purposes adds extra padding overhead. Thus, in many applications, parallel error-checking circuits must be able to generate CRC values for data packets that are not a multiple of some word size. Error-checking circuits that process variably sized data packets are typically more complex because the error-checking circuitry must account for partial data words at the end of the packet.
According to one conventional parallel method, CRC error-checking involves the use of a two-part circuit. A first part of the circuit processes equally sized words of the data packet in parallel to generate successive, residual CRC values. In general, design and development of the first part of the CRC error-checking circuit is reasonably straight-forward because the first part of the error-checking circuit processes only the equally sized full words of the data packet. If the last word of the data is a partial word, it is padded out to a full word using 1's or 0's. The second portion of the circuit will remove the effect of the padding applied to the final word.